1. Field of the Invention
The present invention relates to a computer implemented design system, more specifically to a computer implemented design system and computer implemented design method for manufacturing a reticle set and an integrated circuit using diagonal wiring techniques.
2. Description of the Related Art
With the increased miniaturization of an semiconductor integrated circuit (semiconductor IC), it becomes difficult to manufacture a semiconductor device on a silicon substrate as designed. Therefore, various methodologies are developed to fabricate the semiconductor device as designed, so as to achieve high manufacturing yield and high reliability of the device.
When producing a mask of the semiconductor IC using fine wiring patterns with a width of not more than 0.2 μm, optical proximity correction (OPC) associated with pattern density is widely applied. As for the so-called “isolated wiring pattern” located in the region with sparse patterns, the wiring pattern width of a reticle is increased here to prevent defects in the course of the process such as the reduction in width of isolated wiring patterns. The defect of the width of isolated wiring patterns exists also in case of the isolated vias connecting different wiring layers. Especially, in designs using a rule with a line width of not more than 0.14 μm, there have been various techniques proposed in OPC such as the replacement of an isolated via with a via pattern optimized in advance.
When connecting wirings of a semiconductor IC, up to this time, only a single via has been used when connecting a wiring layer and another layer. However, in recent years, a measure has been employed that improves the reliability of wiring by arranging a plurality of vias in positions which have less influence on the degree of integration of the semiconductor circuit even if the wiring efficiency is lowered.
In order to manufacture the semiconductor IC as designed and improve the reliability, there is a method of adding dummy patterns to a design pattern after the wiring design. This method assists the manufacturing of the semiconductor IC by generating dummy patterns on a design pattern to keep the density distribution of the pattern uniform in metallic wiring layers. This is generally known as a “metal fill process”. The earlier techniques of the metal fill process are to generate dummy patterns by performing a logical operation of topology for blank area on a design layout or to generate an array of rectangles in the regions without wiring.
There is a demand for a basic cell mounted on the semiconductor IC to have a basic transistor with increased driving capability. The “increase in driving capability” means an increase in the gate width of the transistor. This generates a demand for cell size to be increased. A method of increasing the cell size in a gate width direction to improve the driving capability or a method of increasing the gate length and using bent gates or branch gates inside the cell has up to this time, employed.
However, the aforementioned methods were inadequate as countermeasures were needed to manufacture the semiconductor IC according to design values or increase the amount of production reliability.
In the OPC process which increases wiring width or via size for an isolated wiring generated on an existing pattern, a large amount of data is processed, and this processing time is increased. Using a technique of replacing an isolated via isolated from other wiring with a via pattern optimized in advance on a layout, the processing time can be shortened. However, sufficient examination has not been made on the optical proximity effect on the relationship between an isolated via and other vias in the vicinity of the isolated via. In some cases, the isolated via pattern is reduced in size after exposure, and the yield thereof is lowered.
In the earlier method of connecting wirings, when a plurality of vias are used, a line segment bent at 90 degrees is generated in any one of the wiring layers. To delineated the angle of 90 degrees according to the design value, various measures have been performed by OPC, mask data preparation (MDP), or the like. However, roundness is produced in the portion bent at 90 degrees on the substrate actually formed. Therefore, when metallic wirings of upper and lower wiring layers are connected by use of a plurality of vias, a phenomenon, which is called as “shortening”, occurs in which a metallic wiring does not reach the place where a via is located, thus causing a connection defect.
The method of performing logical operations of a layout topology desired to be designed to generate dummy patterns in a region with no wiring, is effective in the case where the object figures are basically rectangles. However, when a number of diagonal figures are included in the design pattern by employment of the diagonal wiring, simple topological operations generate controversial figures in the course of the process. Therefore, a further process is required to modify the controversial figures, thus the process becomes complicated. The method of arranging rectangles in an array cannot generate any desired dummy patterns but in some cases it can, depending on the combinations with a diagonal figure.
By the earlier technique to increase the cell size in the gate width direction to improve the driving capability or the earlier technique to increase the cell length in the gate length direction and to employ bent gates or branch gates inside the cell, the degree of integration of wirings arranged in each cell is lowered.